Description
The GE DS200FCGDH1B is a specialized Gate Distribution and Status (FCGD) printed circuit board manufactured by General Electric for the Speedtronic Mark V and Mark VI turbine control system frameworks. Functioning primarily as a hardware interface module for a six-pulse, phase-controlled, non-reversing Silicon Controlled Rectifier (SCR) bridge system, this board decodes and routes high-speed gating commands. It processes execution signals received from a Digital Signal Processing Card (DSPC) over a standard VME backplane framework and returns multiplexed bridge status feedback to ensure synchronized load commutated inverter (LCI) or drive operations.
Technical Specifications
| Parameter | Value |
| Manufacturer | General Electric (GE) |
| Part Number | DS200FCGDH1B |
| Functional Abbreviation | FCGD |
| System Compatibility | Speedtronic Mark V / Mark VI Control Systems |
| Bridge Topology Interface | 6-pulse, phase-controlled, non-reversing bridge |
| Power Supply Voltage | 24 V DC (Nominal) |
| Number of Channels | 12 channels |
| Feedback Signal Interfaces | Optical fiber connections via 3 onboard FPGA boards |
| Signal Processing Elements | Voltage-controlled oscillators (VCOs) & parallel Sigma-Delta converters |
| Analog Input Span | −8 mV to +45 mV |
| Operating Temperature | −30 °C to +65 °C |
| Physical Form Factor | Dimensions: 9.2 x 6.3 inches; Weight: 0.45 kg |
| Surface Protection | Conformal style PCB protective coating |
Procurement & Commercial Availability
- Condition: New Surplus (Original Box) or Cleaned & Tested Pre-Owned available. Refurbished options undergo rigorous functional component verification before certification.
- Warranty: 12-month standard industrial warranty covering hardware performance under normal operating parameters.
- Lead Time: In-stock configurations generally package and ship within 1 to 3 business days.
- Pricing Notice: Listed marketplace prices are indicative. Unit pricing depends on active global market supply and revision requirements; contact us directly for a firm commercial quote.
Operational Mechanics & Field Constraints
Signal Processing Architecture
The DS200FCGDH1B parses inbound firing commands using a six-entry firing mask register synced directly to the SCR cell strings. For high-accuracy analog feedback paths (monitoring current, voltage, and system flux), the card implements local voltage-controlled oscillators (VCOs) running alongside six parallel Sigma-Delta converters. This redundant processing path allows real-time calculation of V_A, V_B, V_C, and I_A, I_C dynamics to stabilize high-power phase firing configurations.
Hardware Revision Decoding
The specific alphanumeric code DS200FCGDH1B breaks down into critical functional assembly categories:
- DS200: Standard domestic production form factor with conformal protective coating.
- FCGD: Gate Distribution and Status functional board configuration.
- H1: Base hardware assembly group designating specific physical mounting constraints and interface channel footprints.
- B: A “B-level” functional hardware revision. This indicates factory-modified internal component layers designed to solve operational timing problems present in base version cards without changing backward electrical drop-in capability.
Field Commissioning Requirements
When inserting the FCGD card into an active turbine control rack, verify the hardware-level heartbeat sequence. Upon initial host CPU write commands over the VME backplane, an integrated green “IMOK” LED on the board’s front edge must illuminate. If this LED flashes or remains dark while the 24 V DC rail registers within specification, check for configuration mismatches between the primary VME processor’s firmware definition and the card’s revision level.
Frequently Asked Questions
Can a DS200FCGDH1B directly replace an older DS200FCGDH1A or base model?
Yes. The B-suffix represents a backward-compatible functional product revision. It matches the identical form factor, connector positioning, and signaling levels of earlier H1 variations. However, field best practices mandate verifying that the host DSPC card application code does not contain hardcoded hardware-revision safety masks that reject newer component steps.
What causes fiber optic data dropouts on the input interfaces?
The board interfaces with up to three FPGA sub-assemblies via localized fiber optic lines. Signal attenuation often results from particulate ingress inside the onboard optical receivers or tight bend-radius violations within the panel enclosure routing. Ensure all fiber interconnects are clean and maintain a minimum bend radius of 30 mm during panel dress-out.
What is the purpose of the 16-bit up-counter on this card?
The internal 16-bit up-counter operates as a watchdog and diagnostic timer. It continuously counts to its maximum hexadecimal ceiling value of 0FFFFH before cycling back to zero. If a system reset occurs via power interruption or hardware failure, all registries reset instantly to factory baselines to prevent random SCR gate firing.
